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document number: MC33661 rev. 6.0, 11/2006 freescale semiconductor advance information * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2006. all rights reserved. local area network (lin) enhanced physical interface with selectable slew rate local interconnect network (lin) is a serial communication protocol designed to support automotive networks in conjunction with controller area network (can). as the lowest level of a hierarchical network, lin enables cost-effective communica tion with sensors and actuators when all the features of can are not required. the 33661 is a physical layer component dedicated to automotive lin sub-bus applications. it offers slew rate selection for optimized operation at 10 kbps and 20 kbps, fast baud rate (above 100 kbps) for test and programming modes , excellent radiated emission performance, and safe behavior in th e event of lin bus short-to-ground or lin bus leakage during low-power mode. the 33661 is compatible with li n protocol specification 2.0. features ? operational from v sup 6.0 v to 18 v dc, functional up to 27 v dc, and handles 40 v during load dump ? active bus waveshaping offering excellent radiated emission performance ?5.0 kv esd on lin bus pin ?30 k ? internal pullup resistor ? lin bus short-to-ground or high leakage in sleep mode ?-18 v to +40 v dc voltage at lin pin ?8.0 a in sleep mode ? local and remote wake-up capability reported by inh and rxd pins ?5.0 v and 3.3 v compatible digital inputs without any external components required ? pb-free packaging designated by suffix code ef figure 1. 33661 simplified application diagram lin physical interface 33661 ordering information device temperature range (t a ) package MC33661d/r2 - 40c to 125c 8 soicn mcz33661ef/r2 d suffix ef suffix (pb-free) 98asb42564b 8-pin soicn rxd 33661 mcu txd en wake lin inh gnd vsup lin bus v pwr 5.0 v regulator 12 v v dd
analog integrated circuit device data 2 freescale semiconductor 33661 internal block diagram internal block diagram figure 2. 33661 simplifi ed internal block diagram control receiver inh control wake en rxd txd slope control gnd 20 a inh lin 30 k ? vsup
analog integrated circuit device data freescale semiconductor 3 33661 pin connections pin connections figure 3. 33661 8-soicn pin connections table 1. 33661 8-soicn pin definitions a functional description of each pin can be found in the functional pin description section beginning on page page 12 . pin pin name formal name definition 1 rxd data output mcu interface that reports the state of the lin bus voltage. 2 en enable control controls the operation mode of the interface. 3 wake wake input high-voltage input used to wake up the device from sleep mode. 4 txd data input mcu interface to control the state of the lin output. 5 gnd ground device ground pin. 6 lin lin bus bidirectional pin that represents the si ngle-wire bus transmitter and receiver. 7 vsup power supply device power supply pin. 8 inh inhibit output this pin can have two main functions: controlling an external switchable voltage regulator having an inhibit input or driving a bus external resistor in the master node application. 1 2 3 4 5 6 7 8 rxd en wake txd inh vsup lin gnd
analog integrated circuit device data 4 freescale semiconductor 33661 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings power supply voltage continuous supply voltage transient voltage (load dump) v sup 27 40 v wake dc and transient voltage (through a 33 k ? serial resistor) v wake -18 to 40 v logic voltage (rxd, txd, en pins) v log - 0.3 to 5.5 v lin bus voltage dc voltage transient (coupled through 1.0 nf capacitor) v bus -18 to 40 -150 to 100 v inh voltage / current dc voltage dc current v inh i inh - 0.3 to v sup + 0.3 40 v ma esd voltage (1) human body model all pins lin pin with respect to ground machine model v esd1 v esd2 2000 5000 200 v thermal ratings operating temperature ambient junction t a t j - 40 to 125 - 40 to 150 c storage temperature t stg - 40 to 150 c thermal resistance, junction to ambient r ja 150 c/w peak package reflow temperature during reflow (2) , (3) t pprt note 3. c thermal shutdown temperature t shut 150 to 200 c thermal shutdown hysteresis temperature t hyst 8.0 to 20 c notes 1 e sd1 testing is performed in accor dance with the human body model (c zap = 100 pf, r zap = 1500 ? ), esd2 testing is performed in accordance with the machine model (c zap = 220 pf, r zap = 0 ? ). 2 pin soldering temperature limit is for 10 seconds maximum dura tion. not designed for immersion so ldering. exceeding these limi ts may cause malfunction or permanent damage to the device. 3. freescale?s package reflow capability m eets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.freescale.com, search by part number [e.g. remove pref ixes/suffixes and enter the core id to view all orderable parts . (i.e. mc33xxxd enter 33xxx), and review parametrics.
analog integrated circuit device data freescale semiconductor 5 33661 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electric al characteristics characteristics noted under conditions 7.0 v v sup 18 v, - 40 c t a 125 c, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit vsup pin (device power supply) supply voltage nominal dc functional dc, t a 25c v sup 7.0 6.0 13.5 ? 18.0 ? v supply current in sleep mode v sup 13.5 v, recessive state 13.5 v < v sup < 18 v v sup 13.5 v, dominant state or shorted to gnd i s1 i s2 i s3 ? ? ? 8.0 ? 300 12 200 ? a supply current in normal, slow, or fast mode bus recessive, excluding inh output current bus dominant, total bus load > 500 ? , excluding inh output current i s(rec) i s(dom) ? ? 4.0 6.0 6.0 8.0 ma rxd output pin (logic) low-level output voltage i in 1.5 ma v ol 0 ? 0.9 v high-level output voltage v en = 5.0 v, i out 250 a v en = 3.3 v, i out 250 a v oh 4.25 3.0 ? ? 5.25 3.5 v txd input pin (logic) low-level input voltage v il ? ? 1.2 v high-level input voltage v ih 2.5 ? ? v input threshold voltage hysteresis v inhyst 100 300 800 mv pullup current source v en = 5.0 v, 1.0 v < v txd < 3.5 v i pu - 60 - 35 - 20 a en input pin (logic) low-level input voltage v il ? ? 1.2 v high-level input voltage v ih 2.5 ? ? v input voltage threshold hysteresis v inhyst 100 300 800 mv low-level input current v in = 1.0 v i il 5.0 20 30 a high-level input current v in = 4.0 v i ih ? 20 40 a
analog integrated circuit device data 6 freescale semiconductor 33661 electrical characteristics static electrical characteristics lin pin (voltage expressed versus v sup voltage) low-level bus voltage (dominant state) external bus pullup 500 ? v dom ? ? 1.4 v high-level bus voltage (recessive state) txd high, i out = 1.0 a v rec v sup - 1.0 ? ? v internal pullup resistor to vsup (normal mode) r pu 20 30 47 k ? internal pullup current source (sleep mode) i pu ? 20 ? a overcurrent shutdown threshold i ov-cur 50 75 150 ma leakage current to gnd recessive state, 8.0 v v sup 18 v, 8.0 v v lin 18 v gnd disconnected, v gnd = v sup , v lin at - 18 v vsup disconnected, v lin at +18 v i leak 0 - 1.0 ? 3.0 ? 1.0 20 1.0 10 a ma a lin receiver, low-level input voltage txd high, rxd low v linl 0 v sup ? 0.4 v sup v lin receiver, high-level input voltage txd high, rxd high v linh 0.6 v sup ? v sup v lin receiver threshold center (v linh - v linl ) / 2 v linth 0.475 v sup 0.5 v sup 0.525 v sup v lin receiver input voltage hysteresis v linh - v linl v linhyst ? ? 0.175 v sup v lin wake-up threshold voltage v linwu ? 0.5 v sup ? v inh output pin driver on resistance (normal mode) inh on ? 35 70 ? leakage current (sleep mode) 0 v < v inh < v sup i leak 0 ? 5.0 a wake input pin typical wake-up threshold voltage (en = 0 v, 7.0 v v sup 18 v) (5) high-to-low transition low-to-high transition v wuth 0.3 v sup 0.4 v sup 0.43 v sup 0.55 v sup 0.55 v sup 0.65 v sup v wake-up threshold voltage hysteresis v wu hyst 0.1 v sup 0.16 v sup 0.2 v sup v wake input current v wake < 27 v i wu ? 1.0 5.0 a notes 4 this parameter is guaranteed by design; however, it is not production tested. 5 when v sup > 18 v, the wake-up voltage thresholds remain identical to the wake-up thresholds at 18 v. table 3. static electrical characteristics (continued) characteristics noted under conditions 7.0 v v sup 18 v, - 40 c t a 125 c, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 7 33661 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electri cal characteristics characteristics noted under conditions 7.0 v v sup 18 v, - 40 c t a 125 c, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit lin output timing characteristics for normal mode dominant propagation delay time txd to lin (6) measurement threshold (50% txd to 58.1% v sup) measurement threshold (50% txd to 28.4% v sup) t dom ( min) t dom ( max ) ? ? ? ? 50 50 s recessive propagation delay time txd to lin (6) measurement threshold (50% txd to 42.2% v sup) measurement threshold (50% txd to 74.4% v sup) t rec ( min) t rec ( max ) ? ? ? ? 50 50 s propagation delay time symmetry t dom (min) to t rec ( max ) t dom (max) to t rec (min) d t 1 d t 2 - 10.44 - 10.44 ? ? 8.12 8.12 s lin output timing characteristics for slow mode dominant propagation delay time txd to lin (6) measurement threshold (50% txd to 61.6% v sup) measurement threshold (50% txd to 25.1% v sup) t dom ( min ) t dom ( max ) ? ? ? ? 100 100 s recessive propagation delay time txd to lin (6) measurement threshold (50% txd to 38.9% v sup) measurement threshold (50% txd to 77.8% v sup) t rec ( min ) t rec ( max ) ? ? ? ? 100 100 s propagation delay time symmetry t dom ( min ) to t rec ( max ) t dom ( max ) to t rec ( min ) d t 1s dt 2s - 21.88 - 21.88 ? ? 17.44 17.44 s lin output driver fast mode lin fast slew rate (programming mode) fast slew rate dv/dt fast ? 15 ? v/ s lin pin overcurrent shutdown delay time (7) t ov-delay ? 10 ? s lin receiver characteristics receiver dominant propagation delay time (8) lin low to rxd low t rl ? 3.5 6.0 s receiver recessive propagation delay time (8) lin high to rxd high t rh ? 3.5 6.0 s receiver propagation delay time symmetry t rl - t rh t r-sym - 2.0 ? 2.0 s notes 67.0 v v sup 18 v. bus load r 0 and c 0 : 1.0 nf / 1.0 k ? , 6.8 nf / 660 ? , 10 nf / 500 ? . 7 this parameter is guaranteed by design; however, it is not production tested. 8 measured between lin signal threshold v linl or v linh and 50% of rxd signal.
analog integrated circuit device data 8 freescale semiconductor 33661 electrical characteristics dynamic electrical characteristics sleep mode and wake-up timings en pin wake-up time (9) t lwue ? 5.0 15 s wake pin filter time (10) t wf 10 ? 70 s lin pin wake-up filter time (lin bus wake-up) (11) t wuf 40 70 120 s sleep mode delay time (12) en high-to-low t sd 50 ? ? s delay for inh turning off when device enters in sleep mode (16) , (17) en high-to-low and inh high-to-low t sd_inh ? ? 50 s delay time between en and txd for mode selection (13) , (14) t d_ms 5.0 ? ? s delay time between first txd after device mode selection (13) , (14) t d_com 50 ? ? s fast baud rate timing delay entering fast baud rate using toggle function (15) en low to en high t 1 ? ? 35 s delay on en pin resetting fast baud rate to previous baud rate (15) en low to en high t 2 ? ? 5.0 s notes 9 see figures 7 and 8 , 10 . 10 see figures 9 and 10 , 10 . 11 see figures 11 and 12 , 11 . 12 see figure 14 a , 11 . 13 see figures 7 through 12 , pp. 10? 11 . 14 this parameter is guaranteed by desi gn; however, it is not production tested. 15 see figure 13 , 11 . 16 no capacitor is connected to the inh pi n. measurement is done between the en high -to-low transition at 80% of inh voltage. 17 see figure 14 b , 11 . table 4. dynamic electrical characteristics (continued) characteristics noted under conditions 7.0 v v sup 18 v, - 40 c t a 125 c, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 9 33661 electrical characteristics timing diagrams timing diagrams figure 4. normal mode bus timing characteristics figure 5. slow mode bus timing characteristics figure 6. test circui t for timing measurements txd rxd lin v rec t dom (min) recessive state t rl t rh t dom (max) t rec (max) t rec (min) 40% v sup 60% v sup 58.1% v sup 28.4% v sup 74.4% v sup 42.2% v sup dominant state v dom txd rxd lin v rec t dom (min) recessive state t rl t rh t dom (max) t rec (max) t rec (min) 40% v sup 60% v sup 61.6% v sup 25.1% v sup 77.8% v sup 38.9% v sup dominant state v dom lin gnd c 0 r 0 v sup v sup note r 0 and c 0 : 1.0 k ? /1.0 nf, 660 ? /6.8 nf, and 500 ? /10 nf. txd rxd
analog integrated circuit device data 10 freescale semiconductor 33661 electrical characteristics functional diagrams functional diagrams figure 7. en pin wake-up and normal baud rate selection (1.0 kbps to 20 kbps) figure 8. en pin wake-up and slow baud rate selection (1.0 kbps to 10 kbps) figure 9. wake pin wake-up and normal baud rate selection (1.0 kbps to 20 kbps) figure 10. wake pin wake-up and slow baud rate selectio n (1.0 kbps to 10 kbps) figure 11. lin bus wake-up and normal baud rate selection (1.0 kbps to 20 kbps) txd inh en t d_ms t d_com lin t lwue rxd (high z) txd inh en t d_ms t d_com lin t lwue (high z) rxd wake t wf txd inh en t d_ms t d_com lin rxd (high z) wake t wf txd inh en t d_ms t d_com lin (high z) rxd txd inh en wake-up frame t d_ms t d_com lin 0.4 v sup t wuf rxd (high z)
analog integrated circuit device data freescale semiconductor 11 33661 electrical characteristics functional diagrams figure 12. lin bus wake-up and slow baud rate selection (1.0 kbps to 10 kbps) figure 13. fast baud rate selection (toggle function) figure 14. sleep mode enter txd inh en wake-up frame t d_ms t d_com lin 0.4 v sup t wuf (high z) rxd txd en t 1 (35 s) en reset to previous baud rate toggle en = low and txd = high en = high and txd = high t 2 (5.0 s) txd en t sd sleep mode preparation to sleep mode device in communication mode inh en t sd_inh sleep mode preparation to sleep mode normal or slow mode figure 14a figure 14b
analog integrated circuit device data 12 freescale semiconductor 33661 functional description introduction functional description introduction the 33661 is a physical layer component dedicated to automotive lin sub-bus applications. the 33661 features include slew rate selection for optimized operation at 10 kbps and 20 kbps, fast baud rate for test and programming modes, excellent radiated emission performance, and safe behavior in case of lin bus short-to- ground or lin bus leakage during low power mode. digital inputs are 5.0 v and 3.3 v compatible without any external component required. the inh output may be used to control an external voltage regulator or to drive a lin bus pullup resistor. functional pin description power supply pin (vsup) the vsup supply pin is the power supply pin for the 33661. the pin is connected to a battery through a serial diode for reverse battery protection. the dc operating voltage is from 7.0 v to 27 v. this pin sustains standard automotive voltage conditions such as 27 v dc during jump- start conditions and 40 v during load dump. supply current in the sleep mode is typically 8.0 a. ground pin (gnd) in case of a ground disconnection at the module level, the 33661 does not have significant current consumption on the lin bus pin when in the recessive state. (less than 100 a is sourced from lin bus pin, which creates 100 mv drop voltage from the 1.0 k ? lin bus pullup resistor.) lin bus pin (lin) this i/o pin represents the single-wire bus transmitter and receiver. transmitter characteristics the lin driver is a low-side mosfet with internal overcurrent thermal shutdown. an internal pullup resistor with a serial diode structure is int egrated so no external pullup components are required for the application in a slave node. an additional pullup resistor of 1.0 k ? must be added when the device is used in the master node. voltage can go from - 18 v to 40 v without current other than the pullup resistance. the lin pin exhibits no reverse current from the lin bus line to vsup, even in the event of gnd shift or v pwr disconnection. the transmitter has two slew rate selections: 20 kbps (normal slew rate) and 10 kbps (slow slew rate). the slow slew rate can be used to improve radiated emissions. receiver characteristics the receiver thresholds are ratiometric with the device supply pin. data input pin (txd) the txd input pin is the mcu in terface to control the state of the lin output. when txd is low, lin output is low; when txd is high, the lin output transistor is turned off. the threshold is 3.3 v and 5.0 v compatible. the baud rate selection (normal or slow mode) is done at device wake-up by the state of the txd pin prior to a high level at the en pin (see figures 7 through 12 , pp. 10? 11 ). data output pin (rxd) the rxd output pin is the m cu interface, which reports the state of the lin bus volt age. lin high (recessive) is reported by a high voltage on rxd; lin low (dominant) is reported by a low voltage on rxd. the rxd output structure is a cmos-type push- pull output stage. the low level is fixed. the high level is dependant on the en voltage. if en is set at 3.3 v, rxd v oh is 3.3 v. if en is set at 5.0 v, rxd v oh is 5.0 v. in the sleep mode, rxd is high impedance. when a wake- up event is recognized from wake pin or from the lin bus pin, rxd is pulled low to report the wake-up event. an external pullup resistor may be needed. enable input pin (en) the en input pin controls the operation mode of the interface. if en = 1, the interface is in normal mode, with transmission path from txd to lin and from lin to rxd both active. the threshold is 3.3 v and 5.0 v compatible. the high level at en defines the v oh at rxd. the sleep mode is entered by setting en low while txd is high. sleep mode is active after the t sd filter time (see figure 14 , 11 ). inhibit output pin (inh) the inh output pin may have two main functions. it may be used to control an external switchable voltage regulator having an inhibit input. the high drive capability also allows it to drive the bus external re sistor in the master node application. this is illustrated in figures 18 and 19 , 17 . in sleep mode, inh is turned off. if a voltage regulator inhibit input is connected to inh, the regulator will be disabled. if the master node pullup resistor is connected to inh, the pullup resistor will be disabled from the lin bus.
analog integrated circuit device data freescale semiconductor 13 33661 functional description functional pin description wake input pin (wake) the wake pin is a high-voltage input used to wake up the device from the sleep mode. wake is usually connected to an external switch in the application. the typical wake thresholds are v sup / 2. the wake pin has a special des ign structure and allows wake-up from both high-t o-low or low-to-high transitions. when entering into sleep mode, the lin monitors the state of the wake pin and stores it as a reference state. the opposite state of this refe rence state will be the wake-up event used by the device to enter again into normal mode. an internal filter is implemented (40 s typical filtering time delay). wake pin input structur e exhibits a high impedance, with extremely low input current when voltage at this pin is below 14 v. when voltage at the wake pin exceeds 14 v, input current starts to sink into the device. a serial resistor should be inserted in order to limit the input current mainly during transient pulses. recommended resistor value is 33 k ? . important the wake pin should not be left open. if the wake-up function is not used, wake should be connected to ground to avoid false wake-up.
analog integrated circuit device data 14 freescale semiconductor 33661 functional device operation operational modes functional device operation operational modes as described below and depicted in figure 15 and table 5 on 15 , the 33661 has two operational modes, normal and sleep. normal mode may be adjusted to improve radiated emissions by changing the slew rate of the lin bus output to fast or slow mode. in additi on, there are two transitional modes: awake mode, which allows the device to go in normal or slow mode, and wait slow mode, which is a temporary state before the device enters the slow mode. normal mode in the normal mode, the 33661 has slew rate and timing compatible with the lin protoc ol specification and operates from 1.0 kbps to 20 kbps. this mode is selected after sleep mode by setting the txd pin high prior to setting en from low to high. once normal mode is selected, it is impossible to select the slow mode unless the 33661 is set to sleep mode. slow mode in the slow mode, the slew rate is around half the normal slew rate, and bus speed operation ranges from 1.0 kbps to 10 kbps. the radiated emission is significantly reduced compared to the already exce llent emission level of the normal mode. slow mode is entered after sleep mode by setting the txd pin low prior to setting en from low to high. once the slow mode is selected, it is impossible to select the normal mode unless the device is set to sleep mode. fast mode in the fast mode, the slew rate is around 10 times faster than the normal mode. this allows very fast data transmission (> 100 kbps) ? for instance, for electronic control unit (ecu) tests and microcontroller program download. the bus pullup resistor might be reduced to ensure a correct rc time constant in line with the high baud rate used. fast mode can be selected from either normal or slow mode. fast mode is entered vi a a special sequence (called toggle function) as follows: tx d and en pins set low, then txd pulled high, and at the en pin low-to-high transition, the device enters into the fast baud rate. the duration of this sequence must be less than 35 s. the toggle function is described in figure 13 , 11 . once in the fast mode, two different procedures will bring the device back to the previously selected mode (normal or slow): ? the toggle function already described. ? a glitch on en where t 2 < 5.0 s also resets the device to the previously selected mode (normal or slow) ( figure 13 ). sleep mode in the sleep mode, the transmission path is disabled and the 33661 is in low power mode. supply current from v sup is very low. wake-up can occur from lin bus activity from node internal wake-up through the en pin and from the wake input pin. in the sleep mode, the 33661 has an internal 20 a pullup source to vsup. this avoids the high current path from the battery to ground in the event the bus is shorted to ground. (refer to succeeding paragraphs describing wake-up behavior.) device power-up (awake transitional mode) at power-up (v sup rises from zero), the 33661 automatically switches to the awake transitional mode. it switches the inh pin to high state and rxd to low state. the mcu of the application will then confirm normal or slow mode by setting the txd and en pins appropriately. device wake-up events the 33661 can be awakened from sleep mode by three wake-up events: ? remote wake-up via lin bus activity ? internal node wake-up via the en pin ? toggling the wake pin remote wake from lin bus (awake transitional mode) the lin bus wake-up is reco gnized by a recessive-to- dominant transition, followed by a dominant level with a duration greater than 70 s, followed by a dominant-to- recessive transition. this is illustrated in figures 11 and 12 on 11 . once the wake-up is det ected, the 33661 enters the awake transitional mode, with inh high and rxd pulled low. wake-up from internal node activity (normal or wait slow mode) the 33661 can wake up by internal node activity through a low-to-high transition of the en pin. when en is switched from low to high, the device is awakened and enters either the normal or the wait slow transitional mode depending on the level of txd input. the mcu must set the txd pin low or high prior to waking up the device through the en pin. wake-up from wake pin (a wake transitional mode) if the wake input pin is t oggled, the 336 61 enters the awake transitional mode, wit h inh high and rxd pulled low.
analog integrated circuit device data freescale semiconductor 15 33661 functional device operation operational modes figure 15. operational and tr ansitional modes state diagram electromagnetic compatibility radiated emission in normal and slow modes the 33661 has been tested for radiated emission performances. figures 16 and 17 show the results in the frequency range 100 khz to 2.0 mhz. test conditions are in accordance with cispr25 recommendations, bus length of table 5. explanation of operational and transitional modes state diagram operational/ transitional lin inh en txd rxd sleep mode recessive state, driver off. 20 a pullup current source. low low x high impedance. high if external pullup to v dd. awake recessive state, driver off. 30 k ? pullup active. high low x low. if external pullup, high-to- low transition reports wake-up. normal mode driver active. 30 k ? pullup active. slew rate normal (20 kbps). high high high to enter normal mode. once in normal mode: low to drive lin bus in dominant, high to drive lin bus in recessive. report lin bus level: ? low lin bus dominant ? high lin bus recessive wait slow recessive state. driver off. 30 k ? pullup active. high high low high slow driver active. 30 k ? pullup active. slew rate slow (10 kbps). high high low to enter slow mode. once in slow mode: low to drive lin bus in dominant, high to drive lin bus in recessive. report lin bus level: ? low lin bus dominant ? high lin bus recessive fast driver active. 30 k ? pullup active. slew rate fast (> 100 kbps). high high low to drive lin bus in dominant, high to drive lin bus in recessive. report lin bus level: ? low lin bus dominant ? high lin bus recessive x = don?t care. power-up sleep awake wait slow normal fast txd high and en low > t 1 ( 35 s) txd high and en low to lin bus or wake pin txd high and en low to high txd low and en low to high txd low and en txd high and en low > t 1 (35 s) txd high en low for t 2 < 5.0 s, then high wake-up low to high toggle function en low for t 2 < 5.0 s, toggle function then high en low for t 2 < 5.0 s, then high en low for t 2 < 5.0 s, then high note refer to table 5 for explanation. high (10 x) fast (10 x) 1.0 to 20 kbps slow 1.0 to 10 kbps
analog integrated circuit device data 16 freescale semiconductor 33661 functional device operation operational modes 1.5 meters, device loaded with 10 nf and 500 ? bus impedance. figure 16 displays the results when the device is set in the normal mode, optimized for baud rate up to 20 kbps. figure 17 displays the results when the device is set in the slow mode, optimized for baud rate up to 10 kbps. the level of emissions is significantly reduced compared to the already excellent level of the normal mode. figure 16. radiated emission in normal mode figure 17. radiated emission in slow mode
analog integrated circuit device data freescale semiconductor 17 33661 typical applications typical applications the 33661 can be configured in several applications. figures 18 and 19 show master and slave node applications. an additional pullup resistor of 1.0 k ? in series with a diode must be added when the device is used in the master node. figure 18. master node typical application figure 19. slave node typical application control receiver inh control wake en rxd txd slope control gnd 20 a inh lin 30 k ? vsup 33661 lin bus 1.0 k ? master node pullup * * optional i/o rxd txd v pwr mcu v dd 12 v 5.0 v regulator > 33 k ? external switch v dd v dd control receiver inh control wake en rxd txd slope control gnd 20 a inh lin 30 k ? vsup 33661 lin bus v dd * * optional i/o rxd txd v pwr mcu > 33 k ? external switch v dd inh v dd 5.0 v 12 v regulator
analog integrated circuit device data 18 freescale semiconductor 33661 packaging package dimensions packaging package dimensions important for the most current revision of the package, visit www.freescale.com and do a keyword search on the 98a drawing number below. d suffix ef suffix (pb-free) 8-pin soic narrow body plastic package 98asb42564b issue u
analog integrated circuit device data freescale semiconductor 19 33661 reference documents package dimensions reference documents table 6. reference documents title literature number local interconnect network (lin) physical in terface: difference between mc33399 and MC33661 eb215
analog integrated circuit device data 20 freescale semiconductor 33661 revision history revision history revision date description of changes 5.0 10/2006 ? implemented revision history page ? updated the freescale format and style ? added mcz33661ef/r2 to the part number ordering information 6.0 11/2006 ? removed peak package reflow temperature during reflow (solder reflow) parameter from maximum ratings on page 4 . added note with instructions from www.freescale.com .
MC33661 rev. 6.0 11/2006 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2006. all rights reserved. how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics of thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http:// www.freescale.com/epp .

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